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BD8112EFV-M
● Protection Sequence
VCC
Technical Note
EN
＊1
VREG
UVLO
VDAC
SYNC
PWM
＊1
＊2
＊2
4.45V
④
SS
ILED1
ILED2
ILED1'
ILED2'
VLED1
①
②
VLED2
1.0 Ｖ
<0.3 Ｖ
VLED1'
>4.5 Ｖ
100ms ＊3
VLED2'
1.7V
0.3V
2.0V
100ms ＊3
VOVP
FAIL1
FAIL2
＊4
③
*1
*2
*3
*4
①
②
③
After VCC voltage reached to operating conditions, set VDAC voltage, and turn on the EN.
After VREG ≧ 4.6V, turn on SYNC and PWM inputs.
Don’t care input sequence PWM and SYNC.
Aprox 100ms of delay when Fosc = 300kHz
When FAIL1 pull-up to outside power supply.
Case for LED2 in open-mode
When VLED2<0.3V and VOVP>1.7V simultaneously, then LED2 becomes off and FAIL2 becomes low
Case for LED1’ in short-mode
When VLED1’>4.5V and VOVP<1.6V simultaneously, then LED1’ becomes off after 100ms approx
Case for LED2’ in short to GND
③ -1 DCDC output voltage increases, and then SS discharges and FAIL1 becomes low
③ -2 Detects VLED2’<0.3V and shuts down after 100ms approx
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? 2010 ROHM Co., Ltd. All rights reserved.
11/22
2011.08 - Rev.C
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